1. Field of Invention
The invention relates to a method and device for burst reading/writing memory data and, in particular, to a method and device for burst reading/writing memory data without the control of the central processing unit (CPU).
2. Related Art
With the rapid development of computer technology, the CPU has evolved from the 8086 16-bit processor to the current 64-bit processor. Its processing speed has a tremendous progress. The existence of double-CPU systems also enhances the processing speed and efficiency a lot.
Although the processing speed of the CPU is noticeably enhanced, the speed of the dynamic random access memory (DRAM) commonly used in computers is far behind the CPU speed. Moreover, the DRAM has to be refreshed before using it. This further lowers the processing speed. To prevent the memory from the bottleneck of CPU data processing, the current CPU's are all equipped with cache memory to temporarily hold required data. The data access speed is enhanced by using the write through or write back technology.
However, the faster the processing speed is, the more likely errors will occur during data access. When a RAM access error occurs, the running program will freeze or even requires the user to restart the system. This will cause a serious loss if the user is editing some important data without saving. It is particularly a serious problem for a large server. Therefore, an error checking and correcting (ECC) function is being developed to avoid such situations.
In a system with the ECC function, the memory has to be refreshed once when the system is started. Suppose in a 64-bit system [64 bits=8 bytes=1 QW(quad word)]. The burst length is 8, and the cache length is 8 QW. The CPU refreshes 4 bytes at a time. With the cache off condition, the CPU has to perform one reading and one writing to refresh each 4 bytes if there are 8 QW (64 bytes) of data. This is because memory with the ECC function has to execute the read-modify-write (RMW) process. The 8 QW data are first read to the north bridge chipset, and then the data written by the CPU are modified. Finally, the 8 QW data are written back to the DRAM. Totally, it involves 16 times of reading and 16 times of writing. Using the write through technology, the 8 QW data are read to the cache before performing 16 times of reading and 16 times of writing. Therefore, it totally needs 17 times of reading and 16 times of writing. With the cache on condition and using the write back technology, the 8 QW data are first read to the cache. The CPU prepares the data to be written and then writes back to the memory. Therefore, it requires one time of reading and one time of writing.
If one applies the above-mentioned methods to a system with more than 1 GB of memory, then the system will waste a lot of time during power on. Therefore, how to burst reading/writing memory data to reduce the system power on time is an important subject in the field.